EDN

VHDL 101 – IF, CASE, and WHEN in a Process

Last time, in the third installment of VHDL we discussed logic gates and Adders. Let’s move on to some basic VHDL structure. All HDL languages bridge what for many feels like a strange brew of ...
EDN

VHDL 101 – Tick Tock Processing Clocks

So far we have been looking at the more basic structure of VHDL and using combinational logic circuits. In this article, however, we will look at how to use and interface clock signals, the beating ...
Design-Reuse

Open-source Framework and Practical Considerations for Translating RTL VHDL to SystemC

SystemC has gained wide acceptance in the design of new digital IPs. However, there are numerous IPs already designed in VHDL. With the advances in SystemC ecosystem, like IEEE standardization, TLM-2 ...
Design-Reuse

Optimization Methodologies for Cycle-Accurate SystemC Models Converted from RTL VHDL

IP design-houses are hard-pressed by their customers to provide SystemC models of their portfolio IPs, despite already existing VHDL views. VHDL IPs can be translated to SystemC, ensuring correctness, ...